Significantly, Nvidia has also joined up even though it does not have a seat on the CXL board. Alibaba, Cisco Systems, Dell EMC, Facebook, Google, Hewlett Packard Enterprise, Huawei Technology, and Microsoft all jumped on the CXL bandwagon early, and together, these companies represent a big portion of the systems ecosystem when gaged by capacity sold or bought. But it sure doesn’t look like it, not with Steve Fields, chief engineer of Power Systems at IBM who also spearheads OpenCAPI, and Gaurav Singh, corporate vice president at Xilinx and who spearheads CCIX, plus Dong Wei, standards architect at ARM Holdings and Nathan Kalyanasundharam, senior fellow at AMD, being four of the five members of the board of the new CXL Consortium, which was launched this week. At some point, these may resolve into a smaller set of transports and protocols that achieve the collective goals of these interconnects. It can be used to hook anything from DRAM to flash to accelerators in meshes with any manner of CPU.Īt this point, all of these interconnects but Nvidia’s NVLink and AMD’s Infinity Fabric has an independent consortium driving their specifications, and more than a few hyperscalers and vendors participate in multiple consortia to keep a hand in all of the different games. The Gen-Z interconnect from Hewlett Packard Enterprise links out from PCI-Express on servers to silicon photonics bridges and switches that hold out the promise a memory centric – rather than compute centric – architecture for systems. OpenCAPI, which is supported on Big Blue’s Power9 processors, relies on special SERDES communication units on the chip that run at 25 Gb/sec and that can support a variant of the CAPI protocol or the NVLink protocol to attach Power9s to Nvidia Tesla GPU accelerators that also support NVLink – and do so in a coherent fashion across these different devices. Other interconnects try to get around some of the limitations of bandwidth or latency inherent in the PCI-Express bus, such as the NVLink interconnect from Nvidia and the OpenCAPI interconnect from IBM. These include the Compute Express Link (CXL) from Intel, the Coherent Accelerator Interface (CAPI) from IBM, the Cache Coherence Interconnect for Accelerators (CCIX) from Xilinx, and the Infinity Fabric from AMD. Others are coming up with their own electrical or optical signaling. Such as doing some form of memory sharing across devices, usually though some sort of coherency mechanism. There are a number of competing and complementary standards that span this middle ground between the processor and adjacent systems, many of which run atop the PCI-Express bus transport but which do more interesting things with it than just hanging storage or networking off the bus. And that is, oddly enough, going to turn out to be a good thing in the long run. Learn how CXL supports dynamic multiplexing between a rich set of protocols that includes I/O (CLX.io, based on PCIe®), caching (CXL.cache), and memory (CXL.mem) semantics.The dividing lines between system buses, system intraconnects, and system interconnects are getting more blurry all the time. The resulting simplified coherence model reduces the device cost, complexity and overhead traditionally associated with coherency across an I/O link. In CXL, the CPU host is primarily responsible for coherency management abstracting peer device caches and CPU caches. This allows both the CPU and device to share resources for higher performance and reduced software stack complexity. Attendees will learn how CXL technology maintains a unified, coherent memory space between the CPU (host processor) and CXL devices allowing the device to expose its memory as coherent in the platform and allowing the device to directly cache coherent memory. It addresses resource sharing and cache coherency to improve performance, reduce software stack complexity, and lower overall systems costs, allowing users to focus on target workloads. The CXL specification delivers breakthrough performance, while leveraging PCI Express® technology to support rapid adoption. Datacenter architectures are evolving to support the workloads of emerging applications in Artificial Intelligence and Machine Learning that require a high-speed, low latency, cache-coherent interconnect. Compute Express Link™ (CXL™) is an industry-supported cache-coherent interconnect for processors, memory expansion, and accelerators.
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